This application claims the priority benefit of Japanese Patent Application No. 2000-82699, filed Mar. 23, 2000, the entire disclosure of which is incorporated herein by reference.
1. Field of the Invention
The invention relates to a speech synthesizer for synthesizing speech and for regenerating speech and, more specifically, to a speech synthesizer being incorporated in an integrated circuit (IC) chip.
2. Description of the Related Art
A sentence comprises phrases. For example, the sentence xe2x80x9cIt is five-twenty P.M.xe2x80x9d can be divided into three phrases, xe2x80x9cit isxe2x80x9d, xe2x80x9cfive-twentyxe2x80x9d and xe2x80x9cP.M.xe2x80x9d. In a speech synthesizer of the related art, these phrases are stored in a data ROM 5, and are synthesized to regenerate speech. FIG. 5 shows a block diagram of a speech synthesizer 1 in the related art, which is incorporated in an IC chip. The speech synthesizer includes an input terminal IN, a latch circuit 2, an address read only memory (ROM) 3, an address counter 4, a data ROM 5, a speech synthesizing circuit 6, a digital/analog converter (DAC) 7, a low pass filter (LPF) 8, and a timing control circuit 9.
The speech synthesizer 1 receives phrase signals at the input terminal IN. Each of the phrase signals designates one of the phrases of the sentence and is supplied from an external device. The input terminal IN is connected to the latch circuit 2. An output terminal of the latch circuit 2 is connected to the address ROM 3. The address ROM 3 designates address areas, each of which corresponds to one of the phrases. An output terminal of the address ROM 3 is connected to a preset terminal of the address counter 4. An output terminal of the address counter 4 is connected to the data ROM 5. The address counter 4 sends addresses, each of which corresponds to one of the phrases, to the data ROM one-by-one. The data ROM stores speech data in Adaptive Differential Pulse Code Modulation (ADPCM) format, and each of the speech data corresponds to the one of the addresses. That is, groups of the speech data, which correspond to a plurality of phrases, are stored in the data ROM 5.
An output terminal of the data ROM 5 is connected to the speech synthesizing circuit 6. An output terminal of the speech synthesizing circuit 6 is connected to the LPF 8 via the DAC 7. The LPF 8 includes a plurality of operational amplifiers and a reference voltage generating circuit 8a. The reference voltage generating circuit 8a generates a signal-ground SG, which serves as a reference voltage for each operational amplifier. The voltage level of the signal-ground is set at xc2xd level of the power supply voltage VDD. An output terminal of the LPF 8 is connected to a speech output terminal OUT. The timing control circuit 9 receives a clock signal which is applied to a clock terminal CK, and then, controls the timing for synthesizing speech in the speech synthesizing circuit 6.
An operation of the speech synthesizer 1 shown in FIG. 5 is explained as follows. First, the phrase signal, which is applied to the phrase input terminal IN, is latched at the latch circuit 2. Then, based on the latched phrase signal, the address ROM 3 selects an address area, which corresponds to the phrase. The address ROM 3 outputs an initial address of the selected address area to the preset terminal of the address counter 4.
The address counter 4 counts up from the initial address, and send a result of the count as a designated address to the data ROM 5. The data ROM 5 sends speech data at the designated address, which corresponds to the phrase, to the speech synthesizing circuit 6.
The speech synthesizing circuit 6 synthesizes the speech data received from the data ROM 5, and expands the synthesized data to PCM data in digital format. Then, the PCM data is outputted to the DAC 7. The DAC 7 transforms the PCM data to an analog signal, and then sends the analog signal to the LPF 8. The LPF 8 filters high frequencies out from the analog signal, and then passes the filtered analog signal to the speech output terminal OUT, whereby an analog speech signal, which corresponds to the phrase, is provided as a result of speech synthesis.
However, since a plurality of synthesized phrases in this manner may be outputted serially, they are unpleasant to hear unless silence for a particular period is inserted between the phrases outputted from the terminal OUT Therefore, in this speech synthesizer of the related art, which is shown in FIG. 5, silence data is stored as a part of each phrase in the data ROM 5 in order to insert silence between the phrases. By reading out the phrase including the silence data, the speech synthesizer shown in FIG. 5 can output pleasant sounding synthesized speech.
However, the data ROM 5 must have a large capacity in order to store the silence data for each phrase therein in the speech synthesizer of the related art. In view of cost-performance requirements, it is desirable that the capacity of the data ROM be reduced while the quality of the sound of the speech synthesizer is maintained.
It is therefore an objective of the invention is to provide a speech synthesizer, in which the memory capacity for storing speech data is reduced without degrading sound quality.
According to one aspect of the invention, the following speech synthesizer is presented to achieve this objective. That is, a speech synthesizer includes a data memory having a plurality of address areas, which stores a plurality of phrases in the address areas, and an address designating circuit designating one of the address areas based on a phrase signal.
Further, the speech synthesizer includes a speech synthesizing circuit generating a speech synthesizing signal based on the phrase, which is stored in the designated area, a digital/analog converter transforming the speech synthesizing signal to an analog signal, and a counter setting a period of silence.
Furthermore, a speech synthesizer includes a silence-input circuit being connected between the speech synthesizing circuit and the digital/analog converter, which supplies a predetermined voltage to the digital/analog converter for the silence period that is set by the counter.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.